;PALASM Design Description

;---------------------------------- Declaration Segment ------------
TITLE    Williams Multigame Control Panel Mux
PATTERN  
REVISION 01
AUTHOR   John Honeycutt
COMPANY  
DATE     05/19/98

CHIP  _cp_mux  PAL22V10

;---------------------------------- PIN Declarations ---------------
PIN  1          SEL2                                             ; INPUT 
PIN  2          SEL1                                             ; INPUT 
PIN  3          SEL0                                             ; INPUT 
PIN  4          /J1U                                             ; INPUT 
PIN  5          /J1D                                             ; INPUT 
PIN  6          /J1L                                             ; INPUT 
PIN  7          /J1R                                             ; INPUT 
PIN  8          /J2U                                             ; INPUT 
PIN  9          /J2D                                             ; INPUT 
PIN  10         /J2L                                             ; INPUT 
PIN  11         /J2R                                             ; INPUT 
PIN  13         /BTN_1                                           ; INPUT 
PIN  17         /THREE_J3_1                        COMBINATORIAL ; OUTPUT
PIN  18         /THREE_J3_2                        COMBINATORIAL ; OUTPUT
PIN  19         /THREE_J3_3                        COMBINATORIAL ; OUTPUT
PIN  20         /THREE_J3_4                        COMBINATORIAL ; OUTPUT

;----------------------------------- Boolean Equation Segment ------
EQUATIONS
THREE_J3_1 = /SEL2 * /SEL1 *  SEL0 * J1L
           +  SEL2 * /SEL1         * J1U
           +  SEL2 *  SEL1 * /SEL0 * J2U
           + /SEL2 *  SEL1         * J1U

THREE_J3_2 = /SEL2 * /SEL1 *  SEL0 * J1R
           +  SEL2 * /SEL1         * J1D
           +  SEL2 *  SEL1 * /SEL0 * J2D
           + /SEL2 *  SEL1         * J1D

THREE_J3_3 = /SEL2 * /SEL1 *  SEL0 * BTN_1
           +  SEL2 * /SEL1         * J1L
           +  SEL2 *  SEL1 * /SEL0 * J2L
           + /SEL2 *  SEL1         * J1L

THREE_J3_4 =  SEL2 * /SEL1         * J1R
           +  SEL2 *  SEL1 * /SEL0 * J2R
           + /SEL2 *  SEL1         * J1R
 
;----------------------------------- Simulation Segment ------------
SIMULATION
TRACE_ON SEL2 SEL1 SEL0 J1U J1D J1L J1R J2U J2D J2L J2R BTN_1 THREE_J3_1 THREE_J3_2 THREE_J3_3 THREE_J3_4
;
;JOUST
;
SETF /SEL2 /SEL1 /SEL0 J1U J1D J1L J1R J2U J2D J2L J2R BTN_1
;
SETF /SEL2 /SEL1  SEL0  J2L  J2R  BTN_1
SETF /SEL2 /SEL1  SEL0 /J2L  J2R  BTN_1
SETF /SEL2 /SEL1  SEL0  J2L /J2R  BTN_1
SETF /SEL2 /SEL1  SEL0  J2L  J2R /BTN_1
SETF /SEL2 /SEL1  SEL0 /J2L /J2R  BTN_1
SETF /SEL2 /SEL1  SEL0  J2L /J2R /BTN_1
SETF /SEL2 /SEL1  SEL0 /J2L  J2R /BTN_1
SETF /SEL2 /SEL1  SEL0 /J2L /J2R /BTN_1
;
;ROBOTRON/SPLAT
;
TRACE_OFF
TRACE_ON SEL2 SEL1 SEL0 J1U J1D J1L J1R J2U J2D J2L J2R BTN_1 THREE_J3_1 THREE_J3_2 THREE_J3_3 THREE_J3_4
;
SETF /SEL2 /SEL1 /SEL0 J1U J1D J1L J1R J2U J2D J2L J2R BTN_1
;
SETF SEL2 /SEL1  SEL0  J1U  J1D  J1L  J1R
SETF SEL2 /SEL1 /SEL0  J1U  J1D  J1L  J1R
SETF SEL2 /SEL1  SEL0 /J1U  J1D  J1L  J1R
SETF SEL2 /SEL1 /SEL0 /J1U  J1D  J1L  J1R
SETF SEL2 /SEL1  SEL0  J1U /J1D  J1L  J1R
SETF SEL2 /SEL1 /SEL0  J1U /J1D  J1L  J1R
SETF SEL2 /SEL1  SEL0  J1U  J1D /J1L  J1R
SETF SEL2 /SEL1 /SEL0  J1U  J1D /J1L  J1R
SETF SEL2 /SEL1  SEL0  J1U  J1D  J1L /J1R
SETF SEL2 /SEL1 /SEL0  J1U  J1D  J1L /J1R
SETF SEL2 /SEL1  SEL0 /J1U  J1D /J1L  J1R
SETF SEL2 /SEL1 /SEL0 /J1U  J1D /J1L  J1R
SETF SEL2 /SEL1  SEL0 /J1U  J1D  J1L /J1R
SETF SEL2 /SEL1 /SEL0 /J1U  J1D  J1L /J1R
SETF SEL2 /SEL1  SEL0  J1U /J1D /J1L  J1R
SETF SEL2 /SEL1 /SEL0  J1U /J1D /J1L  J1R
SETF SEL2 /SEL1  SEL0  J1U /J1D  J1L /J1R
SETF SEL2 /SEL1 /SEL0  J1U /J1D  J1L /J1R
SETF SEL2 /SEL1 /SEL0  J1U /J1D  J1L /J1R /J2U /J2D /J2L /J2R /BTN_1
;
;BUBBLES
;
TRACE_OFF
TRACE_ON SEL2 SEL1 SEL0 J1U J1D J1L J1R J2U J2D J2L J2R BTN_1 THREE_J3_1 THREE_J3_2 THREE_J3_3 THREE_J3_4
;
SETF /SEL2 /SEL1 /SEL0 J1U J1D J1L J1R J2U J2D J2L J2R BTN_1
;
SETF SEL2 SEL1 /SEL0  J2U  J2D  J2L  J2R
SETF SEL2 SEL1 /SEL0 /J2U  J2D  J2L  J2R
SETF SEL2 SEL1 /SEL0  J2U /J2D  J2L  J2R
SETF SEL2 SEL1 /SEL0  J2U  J2D /J2L  J2R
SETF SEL2 SEL1 /SEL0  J2U  J2D  J2L /J2R
SETF SEL2 SEL1 /SEL0 /J2U  J2D /J2L  J2R
SETF SEL2 SEL1 /SEL0 /J2U  J2D  J2L /J2R
SETF SEL2 SEL1 /SEL0  J2U /J2D /J2L  J2R
SETF SEL2 SEL1 /SEL0  J2U /J2D /J2L  J2R
SETF SEL2 SEL1 /SEL0 /J2U  J2D /J2L  J2R /J1U /J1D /J1R /J1L
;
;DEFENDER / STARGATE
;
TRACE_OFF
TRACE_ON SEL2 SEL1 SEL0 J1U J1D J1L J1R J2U J2D J2L J2R BTN_1 THREE_J3_1 THREE_J3_2 THREE_J3_3 THREE_J3_4
;
SETF /SEL2 /SEL1 /SEL0 J1U J1D J1L J1R J2U J2D J2L J2R BTN_1
;
SETF /SEL2 SEL1  SEL0  J1U  J1D  J1L  J1R
SETF /SEL2 SEL1 /SEL0  J1U  J1D  J1L  J1R
SETF /SEL2 SEL1  SEL0 /J1U  J1D  J1L  J1R
SETF /SEL2 SEL1 /SEL0 /J1U  J1D  J1L  J1R
SETF /SEL2 SEL1  SEL0  J1U /J1D  J1L  J1R
SETF /SEL2 SEL1 /SEL0  J1U /J1D  J1L  J1R
SETF /SEL2 SEL1  SEL0  J1U  J1D /J1L  J1R
SETF /SEL2 SEL1 /SEL0  J1U  J1D /J1L  J1R
SETF /SEL2 SEL1  SEL0  J1U  J1D  J1L /J1R
SETF /SEL2 SEL1 /SEL0  J1U  J1D  J1L /J1R
SETF /SEL2 SEL1  SEL0 /J1U  J1D /J1L  J1R
SETF /SEL2 SEL1 /SEL0 /J1U  J1D /J1L  J1R
SETF /SEL2 SEL1  SEL0 /J1U  J1D  J1L /J1R
SETF /SEL2 SEL1 /SEL0 /J1U  J1D  J1L /J1R
SETF /SEL2 SEL1  SEL0  J1U /J1D /J1L  J1R
SETF /SEL2 SEL1 /SEL0  J1U /J1D /J1L  J1R
SETF /SEL2 SEL1  SEL0  J1U /J1D  J1L /J1R
SETF /SEL2 SEL1 /SEL0 /J1U /J1D  J1L  J1R
SETF /SEL2 SEL1 /SEL0  J1U /J1D /J1L  J1R
SETF /SEL2 SEL1 /SEL0  J1U  J1D /J1L /J1R
SETF /SEL2 SEL1 /SEL0 /J1U /J1D /J1L /J1R
SETF /SEL2 SEL1 /SEL0  J1U /J1D  J1L /J1R /J2U /J2D /J2L /J2R /BTN_1

TRACE_OFF
;-------------------------------------------------------------------